The DC ug tells me that "If the performance violates the timing goals by more than 15 percent, you should consider
whether to refine the design budget or modify the HDL code."
But what does this 15% stands for? Dose it mean the violation of the longest critical path is more than 15% of the related clock period?
that's comment just for your paths which >15% violated related clock period.
but actually, not all of violated paths, example, you have a big slack on a path due to a big fanout/slew from pre-CTS --> it's will gone when post-CTS. no need "refine the design budget or modify the HDL code"