chandru4u4
Newbie level 3
hello every one...
I am working in xilinx ...artix 15t fpga . In this i need to know , in below two process what value will there in "addr" varible in first rising edge ....kindly reply any one ...both clk is same
initi...addr<=0;
-----Process-1------
rising edge of clk
temp<=ram(addr);
end process
-----Process-2------
rising edge of clk
addr<=addr+1;
end process
I am working in xilinx ...artix 15t fpga . In this i need to know , in below two process what value will there in "addr" varible in first rising edge ....kindly reply any one ...both clk is same
initi...addr<=0;
-----Process-1------
rising edge of clk
temp<=ram(addr);
end process
-----Process-2------
rising edge of clk
addr<=addr+1;
end process