VHDL is not a programming language - it is meant to model hardware.
The way signals work in VHDL is that the are scheduled to update at some future point in time. if no time is specified (with an after clause) then it will be updated at the end of the current delta cycle. All processes trigged on the rising edge of the clock will process in 0 time in the same delta cycle, so nothing will have updated yet. All of your assignments, a,b,c,d and temp will be assigned at the end of the current delta.