When should we use bit and when std_logic in VHDL?

[deepu_s_s]

Hello Friends,

When should we use bit and when std_logic

Thanks and Regards
Deepak

 

[FvM]

Re: Doubt in VHDL

Most libraries and IP cores are based on STD_LOGIC and it's aggregates. There is no purpose to use BIT normally, I think. As long as you don't see a particular need...

 

[deepu_s_s]

Doubt in VHDL

what should i tell if a interviewer asks me this question. how should i answer him

 

[sau_sol]

Re: Doubt in VHDL

BIT has only two logics i.e 1 and 0

but BIT_LOGIC has 9 logics these are
0 - - strong 0
1 - - strong 1
X - - strong unknown
L - - weak 0
H - - weak 1
W - - weak unknown
U - - Uninitialize
Z - - high impedence
'-' - - dont care

so practically any of the above can occur so we use std_logic

this is the correct explanation.

 

[amir81]

Doubt in VHDL

the most important character of std_logic is defined in its resolution table.
when you wire (ie: wired and) two signal with different logic level its important to know what is the result.
refer to ieee standard for this table.