when should use negative supply voltage?

[prcken]

I saw in some of the HBT circuits design in BiCMOS process uses ground and negative power supplies, I am just wondering why.

 

[erikl]

To reduce power consumption. With negative body supply (i.e. positive supply "rail" for NMOS sources and NPN emitters = GND) you can save power at comparable operation frequencies.

 

[prcken]

Hi erikl,
I still couldn't understand how to save power, e.g. in the below picture, the current source and the supply potential are fixed, so that the static power consumption is fixed, too. It seems nothing to do with positive and negative power supplies.
Thanks!

 

[erikl]

Hi prcken,

I think this circuit has nothing in common with "negative power supply on substrate": Q7 and its companion are just constant (tail) current supplies for the Master-Slave-FF. ECL logic architecture, I guess, as the positive power supply is called "Ground".

 

[prcken]

Hi prcken,

I think this circuit has nothing in common with "negative power supply on substrate": Q7 and its companion are just constant (tail) current supplies for the Master-Slave-FF. ECL logic architecture, I guess, as the positive power supply is called "Ground".

I agree, thanks!

 

[erikl]

In my 1^st answer (above) I misunderstood your question, sorry. (I thought of negative body biasing for power reduction, used in many microprocessors).

Your circuit probably is an ECL-compatible architecture; usual ECL system power supply is Ground and -5.2V .

 

[prcken]

Thanks!
True, they are designed for ECL, i found a note explains the ECL and Positive supply ECL (PECL).
I will just design for positive voltage for my own test.

 

[erikl]

I will just design for positive voltage for my own test.

Right.
On the other hand: it doesn't matter how you name your power supply terminals. And you may assign different names internally and externally.