When is it nessasary to use the VHDL null statement?

[shaiko]

Hello,

Are there any cases when the use of a VHDL "NULL" statement is mandatory?
I.E - when not using it will result in the synthesis of different logic...

 

[TrickyDicky]

No.
You would only use null when you wanted nothing to happen. In synthesisable logic its mostly just used to explicitly show you want nothing to happen, but its not mandatory.

In testbenches, it is very useful though, as it is the default assignment of an access type.

 

[SynthWorks]

Null statement is roughly equivalent to a book having, "This page intentionally left blank."

That said, when a case target has no other code, it is nice to put "NULL ; " there as then in the future, when someone else is working on the next revision of the design, they know that they did not accidentally delete something.

 

[shaiko]

it is nice to put "NULL ;"

Yes, I understand that. writing comments in your code is also nice...

Is it ever mandatory to use "null"? if it is, please post an example...

 

[TrickyDicky]

Is it ever mandatory to use "null"? if it is, please post an example...

There are no cases for synthesisable VHDL where null is mandatory.

 

[shaiko]

There are no cases for synthesisable VHDL where null is mandatory.

Can you post a code example that shows when it's necessary to use "null" in simulation?

 

[TrickyDicky]

About the only time you need it is when checking that an access type has been allocated memory or not:

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Code VHDL - [expand]
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type my_access_t is access integer;
variable ptr : my_access_t;
 
.....
 
if ptr = null then
  ptr := new integer'(7);
end if;

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