When I double the width & length of input pair the phase margin changes from 60 to 40
I design a opamp, when I double the width and length of input differential pair, the phase margin changed from 60 degree to 40 degree,
can anyone tell me the reason?
thank you
You'd better specify the configuration of your OPamp.
Say,the folded cascode configuration,the Cgd of the input transistor will lower the 2nd pole,thus the PM.
the opamp is folded cascode, at first I think it is the cgd of input pair that degrade phase margin, but the cgd is 20f and gm=0.5u, this zero is about 4G and the unity gain bandwidth of opamp is 200M, so the cgd influence is small.
but beside this reason I cannot find other reason,
maybe leakage? my process is 90nm!
the dominant pole is at output,ya,input cgd's influence is small.make sure your dc bias makes every mosfet work at saturate region.and the unity gain frequency is 200M,do you need so large bandwidth?
Hi qqic: I think you increase the w and l of the input transistor, then the input capacitance will increase, so the second pole i.e. gm/c will decrease, so the phase margin become worse!
Hi all,
I know the reason,when input pair W*L increase, the cds increase quickly! from the DC operation point: cds=72f
cdg=-72.5f
cgd=-10.7f
cgs=-120f
I have 2 questions:
1> why the cdg is minus in DC simulation of spectre ?
2> why cgd is not the same to cdg, and cdg is much high?
3> why cds is much high? in my opinion cds should be very small?