Till Now what I read and saw only set up time to decide frequency(hold time too but I have no Idea on that) or set up time violations .............But I want to know when does hold time vioaltions come into picture.In which case violations may occur?Can anyone get some points here ................
The hold time is the amount of time that data input signals are to be held past the clock rising edge or falling edge. From the defination, you can see hold time mainly constrain the propagation delay of flip-flop. hold time violation may occur when you have combination logic between two flip-flop. and even some feedback circuit in your logic.
Hi,
In setup window the logic is evaluated when clock edge comes, to make evaluated data stable the input must be stable after clock edge.
Itz based on charging or discharging and logical effort of mosfets(Needs backend basics)