When do hold time violations occur?

[verilog_always]

Till Now what I read and saw only set up time to decide frequency(hold time too but I have no Idea on that) or set up time violations .............But I want to know when does hold time vioaltions come into picture.In which case violations may occur?Can anyone get some points here ................

 

[shockie]

Hold time

The hold time is the amount of time that data input signals are to be held past the clock rising edge or falling edge. From the defination, you can see hold time mainly constrain the propagation delay of flip-flop. hold time violation may occur when you have combination logic between two flip-flop. and even some feedback circuit in your logic.

 

[tronix]

Re: Hold time

hello
One just have to ensure that hold time is not violated.If it is violated then the circuit will not work even at a very low frequency.




tronix

 

[aslijia]

Hold time

if you have more than twe flip-flop tail-to-tail connect together, it may cause hold time violate.

 

[ankit12345]

Hold time

If input signal is not stable in hold time.....then the FF goes into metastability.....WHY?

 

[satyakumar]

Re: Hold time

Hi,
In setup window the logic is evaluated when clock edge comes, to make evaluated data stable the input must be stable after clock edge.
Itz based on charging or discharging and logical effort of mosfets(Needs backend basics)

 

[vinod_g]

Re: Hold time

when the data is not stable after the clock for some time then hold time violations occurs

 

[wice]

Hold time

usually ,the reason why hold violation happened is that the clock skew is bigger than data path delay .

 

[cnspy]

Hold time

Most time try to clear the hold violation, just insert the buffer to delay the signal change.

 

[muralinelavalli]

Hold time

The hold time is the amount of time that data input signals are to be held past the clock rising edge or falling edge. From the defination,