Nov 28, 2012 #1 S shaiko Advanced Member level 5 Joined Aug 20, 2011 Messages 2,644 Helped 303 Reputation 608 Reaction score 297 Trophy points 1,363 Activity points 18,302 Is it true that a VHDL "for loop" can only be used inside a procedural statement ? (like a "process") and never as a concurrent statement ?
Is it true that a VHDL "for loop" can only be used inside a procedural statement ? (like a "process") and never as a concurrent statement ?
Nov 28, 2012 #2 B bking Member level 5 Joined May 15, 2012 Messages 85 Helped 28 Reputation 56 Reaction score 28 Trophy points 1,298 Location Maryland, USA Activity points 1,765 Inside: Process, Procedure, or Function page 32 -> https://www.csee.umbc.edu/portal/help/VHDL/VHDL-Handbook.pdf Added: or with a Generate statement
Inside: Process, Procedure, or Function page 32 -> https://www.csee.umbc.edu/portal/help/VHDL/VHDL-Handbook.pdf Added: or with a Generate statement
Nov 28, 2012 #3 T TrickyDicky Advanced Member level 7 Joined Jun 7, 2010 Messages 7,110 Helped 2,081 Reputation 4,181 Reaction score 2,048 Trophy points 1,393 Activity points 39,769 bking said: Added: or with a Generate statement Click to expand... That is a for-generate statement, not a for loop. Shaiko - the answer is yes.
bking said: Added: or with a Generate statement Click to expand... That is a for-generate statement, not a for loop. Shaiko - the answer is yes.
Nov 28, 2012 #4 S shaiko Advanced Member level 5 Joined Aug 20, 2011 Messages 2,644 Helped 303 Reputation 608 Reaction score 297 Trophy points 1,363 Activity points 18,302 Following this, Please give your input regarding this post: https://www.edaboard.com/threads/272917/