hello , when i do gate simulation , and i found a question . A pin input a high-Z to a DFF , and the DFF output a X to the next circuit. But I think the model of DFF is wrong , and i think that when a DFF input a high-Z the output should be 0.
How do you think?
simly exam:
high-Z is between '1" and "0",
the gate only take the "1" or "0" as valid input,
so it don't know what to do, so the output is ,"unknown", x statement.
In real circuits, the output may be 0 or 1, so the model is absolutely correct.
actually if we input a Z to a inverter, the output also should be X.
best regards
stormwolf said:
hello , when i do gate simulation , and i found a question . A pin input a high-Z to a DFF , and the DFF output a X to the next circuit. But I think the model of DFF is wrong , and i think that when a DFF input a high-Z the output should be 0.
How do you think?
so this means it's unknown
i'm a bit confused now between unknown and don't care
are they the same
or don't cares are only for karnough maps and boolean algebra in general
while unknown shows only in simulation results
If the FF model is correct. I think you need a good initialization in your simulation setup so that after POR, all of the internal signals are in know states.
the model is right.
when you input a "z" to dff, in general the model should output "x".
your design should avoid this case, that means you should give all the input of dffs in your design a certain value.
especially, take care about the memory output to your logic when it has not bus holder,
The simulator looks at UDP (in case of verilog) or VITAL model (in case of vhdl) of the D Flip flops in the simulation models of the library (for example .sim file of the library vendor's library). It just goes by what model says. The UDP or VITAL models are the ultimate judge. Hope it clears the doubts about Z ..etc.