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I think they are used for DRC reasons and also to provide continuity of the PAD ring ( connect the vdd and ground rails of ESD protection devices ) all around the chip
Yes, it's correct.. for PAD ring continuity, we use IO filler cells.
But we also use filler cells in the std cell region(inside core area). The reason is to fulfill the continuity of N-Well throught the std cell area. Some of the small cells also doesn't have the bulk connection (substrate connection) because of their small size. In those cases, the abutment of cells through inserting filler cells can connect those substares of small cells to the power/ground nets.
Of course some of the filler cells are used to make up the poly density (if that filler cell is having any poly structure inside).
BTW, it's always better to fill the gaps with fatter filler cells first then thinner filler cells.
And some libraries have spare cells embedded inside filler cells. Good for ECO....
filler cells are cells that generally contains substrate contacts and ESD circuits.
consider the case of memories, in the core array after a number of cells we place these filler cells,
they play a very important role here, as core cells are designed for minimum area and even are drc violated, so after a set of core cells we place these filler cells to provide the substrate contacts only.
1) these substrate contacts absorbs the noise transients. and
2) prevents the latchup.
and in the rest of memory these filler cells contain ESD logic and substrate contacts.
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