Paul,PaulHolland said:Hi,
Why on transistor level ???.. The main component in final PN I already gave you the rest if of minor importance in most cases unless you are making a system with a PN of -140 dBc...
regards,
Paul.
amitbhaiji said:With hspice we cannot simulate the phase noise. But one can use hspice to simulate the transistor level jitter ( Both long term and shot term jitter using the eye diagram plot). and then using some mathamatical modelling and intepolation be can obtained the phase noise plot of either the pll or the oscillator.
Amit
khouly said:i think ordinary spice simulators cannot simulate phase noise performance of the pll
some simulators with RF cababilities , can like specterRF , ELDORF, ADS2002, 2003 can do the job also
zyyang said:for the clock generator, may be we consider on the jitter more, but if you must pay attention to PN, may be there is no business simulator for simulate the phase noise of pll. you should simulator the phase noise of sub-modules like pfd+charge pump, loop filter, vco, reference and divider, then use the mathmatical model(not linearity) to calulate the whole phase noise. By the way, the phase noise of sub-modules can be simulated by hspiceRF if you must use spice.
Regards
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