tie off cell
Tie-off cells provide ESD protected logic levels '1' and '0' to be used for connecting transistor gates.
the transistor gates in a design may be required to connect logic '1' and logic '0' permanently, ie VDD and VSS logic levels,
It is usually tapped from near by Power lines.
But to ensure the Transistor gate recieves only ESD protected signal, the Tie-off cells are placed between these gates and power line.
These cells are part of standard cell library.
soc encounter has the option for connecting Tie-off cells to the design.