Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Re: what's the "logical tie-off cells" in soc enco
This is also termed as Tie high cells (which is tied to Vdd 5v always)
and Tie low cells( Which will be always tied to VSS or 0V always)
The gate of transistor may turn on or turn –off due to power and ground bounce. Due to this problem occurs. So if a gate has to turn on only on VDD it must be brought near Pcells. This is called Tie_high
if a gate has to turn off only on Vss it must be brought near N_cells. This is called Tie_low. This Pcells and Ncells are a part of Standard cell library.