"DSP soft core" is it, floating point processing unit in a soft core CPU like MicroBlaze?
If so, I am afraid of it's out of consideration, since I need deterministic latency.
FPGA vendors have log() and exp() floating point IP with single or double accuracy. They should work for the application. I expect that they are using some kind of "hybrid" algorithm, combination of tables with interpolation and separate handling of exponents.
FPGA vendors have log() and exp() floating point IP with single or double accuracy. They should work for the application. I expect that they are using some kind of "hybrid" algorithm, combination of tables with interpolation and separate handling of exponents.