1.source follower? kind of weird, i dont think level shifter works under saturation region. It's more like a digital cell, with its node voltage switching between VDD and 0v.
2.positive feedback... nah, the first one IS a positive feedback circuit too.
3.My opinion is, the second lv shifter will have much less leakage current from VDD to gnd.
look at the left side of the 1st circuit.
if you send a clock signal at vin,
the pmos at left top(say MP1) and the nmos at left down(sayMN1) would conduct at same time,and a huge current will flow from VDD to GND. you can run transient simulation, and probe I(MP1) and I(MP2) .
for the 2nd circuit ,now we have MP1,MP2,MN1 at left side(from top to bottom). Even a clock signal at Vin,these three mos are almost unlikely to turn on at same time, so there wont be a direct current path from VDD to GND.
This helps to reduce current consumption,especially when you use a lot of clock drived lv shifter in your circuit.