Re: verilog hdl or vhdl?
Verilog is easier to understand and use. For several years it has been the language of choice for industrial applications that required both simulation and synthesis. It lacks, however, constructs needed for system level specifications. VHDL is more complex, thus difficult to learn and use. However it offers a lot more flexibility of the coding styles and is suitable for handling very complex designs
Pls see the link for complete description
Verilog vs. VHDL: VHDL & Verilog Compared & Contrasted
Plus Modeled Example Written in VHDL, Verilog and C
h**p://www.angelfire.com/in/rajesh52/verilogvhdl.html