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Custom trace between Ethernet PHY and Switch

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This is with respect to my earlier question on LAN8840 PHY and KSZ9567 Switch.

Port 6 of the KSZ9567 is RGMII connected to LAN8840.

The Module 3 of this errata of KSZ9567 (https://ww1.microchip.com/downloads...cuments/Errata/KSZ9567R-Errata-DS80000755.pdf) states that there's a timing errata with Port 6.

The datasheet says the setup time must be a minimum of 2.2ns for Data to clock.
The KSZ Ingress delay can only be set to 1.3ns (Note that the register description mentions 1.5ns but it is 1.3ns – Note 6-5 under RGMII timing values).

Therefore, using this delay, I still need a minimum additional path delay of 0.9ns to achieve a minimum setup time of 2.2ns.

This appears to be tough in PCB for me.

For this, I am not using the chip delay on the KSZ9567. I am trying to work on the egress delay with LAN8840 (https://ww1.microchip.com/downloads...s/DataSheets/LAN8840-Data-Sheet-00004727A.pdf) page 49.

So, the Plan is to use the LAN8840 fixed 2ns (typ) delay to TXC input as well as add a small (0.2 -0.4ns) Pad Skew delay to make up the 2.2ns min. DS pg 44.

Would this be fine?
 

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