What's the difference between unsigned (7 to 0) and std_logic_vector (7 to 0)?

[rajakash]

hi friends

wat s the difference between
unsigned(7 downto 0)
std_logic_vector(7 downto 0);

 

[btminzon]

Re: difference

Hey rajakash, Unsigned is internally treated like a number, and, of course, unsigned, range 0 to 255. std_logic_vector, is a vector, and you can assign, for example, a don´t care ('X') a tri-state ('Z'), and take one bit indepenently, for example, if you want the 4 bit, you can assign: test_vector <= test(4) --test_vector receives the 4th bit. any doubt, just ask!!!

regards

Breno

 

[salma ali bakr]

Re: difference

a std_logic_vector is converted to an unsigned (or a signed) for performing mathematical operations on it...