Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Whats the difference between SET_FALSE_PATH and SET_IDEAL_ne

Status
Not open for further replies.

hellowater

Newbie level 1
Joined
Oct 29, 2007
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,288
set_ideal_network

Which constraint should i set on a port/pin/wire which has a very large fanout?
SET_FALSE_PATH or SET_IDEAL_NETWORK?

What is the difference between SET_FALSE_PATH and SET_IDEAL_NETWORK.?

And, what about another command "set_disable_timing"?

thanks!
 

shelby

Full Member level 2
Joined
Jan 4, 2007
Messages
124
Helped
38
Reputation
74
Reaction score
18
Trophy points
1,298
Activity points
2,045
set_false_path

For large fanout nets, use set_ideal_network. This should be done during synthesis, before running clock tree sythesis. During CTS you also need to buffer your high fanout nets.

set_false_path on a pin/port/net is used when you don't care about timing through that path.

set_disable_timing is used for disabling timing arcs through cells which are not real or you don't care about.
 

iwpia50s

Full Member level 4
Joined
Oct 31, 2007
Messages
223
Helped
27
Reputation
54
Reaction score
10
Trophy points
1,298
Activity points
2,305
set_disable_timing set_false_path

Regarding shelby's reply, you should set your HFN to be ideal before synthesis, but it doesn't matter for cts because cts will only build a buffer tree for what is defined as a clock.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top