synthesis driving_cell
thanku u,no_mad!
that means the driving_cell will use a default zero input transtion to calculate his output transition which used as the input transition of the input pin of the design.
i still can't understanding this:
The portion of the driving cell delay caused by the net will be included as a port delay on the input port.
before layout we will set_input_delay on the input pin of the design,after layout still work?or it will override the net'RC delay on the input pin?
how about set_drive?i still unknow how to use the set_drive to get the input transition of input pin.
best regard