bufferable
There is nothing much to know with respect to this!! but if it is a bufferable it specifies that the final destination of the the current transfer can be delayed (for example if final destination is to some usb or network from the processor it can be delayed to perform appropriate transfers.
And suppose if it is a cacheable then the transaction when it has reached to the final destination need not match with the initial transfer started by the processor/Master. The data can also be mixed with from different transactions to form a packet(this mix may be used to form a packet/frame) accordingly.
not all master's(ahb) will support this kind of transfers, here slave can use the transfers accordingly.
Thanks & Regards