I don't know if I'm making progress or heading straight into a dead end:
For single signals where I need to constrain the skew, creating a skew group from the source pin in questions gives messages to suggest that creating a clock tree might be in order. So I create a clock tree instead of a skew group, and the skew group is automatically created.
I can set the constraints I require, but they are ignored.
Looking into the database, I can see that all pins are ignored, i.e. in .cts_sinks, but not in .cts_active_sinks.
When creating the clock tree, I get
Found 78 implicit ignore or stop or exclude pins - run report_clock_trees -list_special_pins for more details.
So I run the command as suggested to get
test_I/g1060__3377/SEL implicit ignore
and
test_I/sclk_reg[0]/D implicit exclude
So I "just" need to find out why the pins are ignored. The obvious answer is "because they are not clock inputs". These are multiplexer select pins.
I'm looking through the help and database properties, but so far failed to come up with the solution. cts_ignore_pins sounds interesting, but is empty.
digitalo
- - - Updated - - -
OK, this seems to work: I try to force all connected pins to the "stop" sink type.
create_clock_tree_spec
set_db net:TEST .loads.cts_sink_type stop
create_clock_tree -source TEST
set_db skew_group:TEST .cts_target_skew 0.2
I still have to check in detail how the real case looks, but at least I get a sensible tree and a skew report.