Thanks all for your reply.
To clarify the question for giri_lp, the NMOS caps I mentioned are not parasitic caps, they are sort of varicaps.
There are two kinds of connection methods:
1) Drain/Source/Bulk connected together, cap voltage applied to Gate and D/S/B;
2) Drain/Source float, cap voltage applied to Gate and Bulk connected to GND.
Say we use 2nd connection method to get an accumulation-mode NMOS cap (in a linear region), so from parasitic point of view, NMOS in NWELL will have more parasitic (due to NWELL to substrate cap) than NMOS in PWELL? I can think of NMOS in PWELL (no deep NWELL) has more noise because the all the noise will be injected to P-BULK. Am I right? Any other advantage/disadvantage? Any consideration from layout point of view?
Thanks,
Lynda