What's the advantage & disadvantage of using NMOS and PMOS cap in analog IC circuit?

[lyndafan]

What's the advantage & disadvantage of using NMOS and PMOS cap in analog IC circuit?

Dear Sir/Madam,

My question is: what's the advantage and disadvange of using NMOS and PMOS cap in analog IC circuit? What's the advange of using NMOS cap in NWELL or PWELL? It would be nice if some applications (examples) are given as well.

Thanks,
Lynda

 

[giri_lp]

nmos in n well+capacitor

What you mean by NMOS cap, PMOS cap? load capacitances are diffarent from parasitic caps.

DO clarify here

 

[VASANSNS]

nmos cap in nwell

Are you talking about the Gate to substrate capacitance, keeping the source and drain terminals open ?

 

[navidsar]

nwell substrate cap

Dear Lynda,

when we use NMOS or PMOS caps, it is desired that they work in a linear region. This happens when they are in accumulation region. Then in normal implantation of them, we should have enough voltage across them to provide accumulation.
In case we make an NMOS in NWELL, there is already accumulation in channel. Then you don't need to put voltage across the cap. I guess this is also the case for PMOS in PWELL which I have not seen yet :|
there is also some disadvantages for NMOS in NWELL like the parasitic caps from NWELL to substrate.
I have recently encountered an example for this which I have written the reference for you:
Robert H.M. van Veldhoven, "A triple-mode Continuous-Time Sigma-Delta Modulator with Switched-Capacitor Feedback DAC for a GSM-EDGE/CDMA2000/UMTS Receiver" IEEE Journal of Solid-State Circuits, VOL. 38 NO.12, December 2003.
you can find the topic about cap on page 2073...

good luck
- Navid

 

[lyndafan]

nmos in nwell gate capacitor

Thanks all for your reply.

To clarify the question for giri_lp, the NMOS caps I mentioned are not parasitic caps, they are sort of varicaps.

There are two kinds of connection methods:
1) Drain/Source/Bulk connected together, cap voltage applied to Gate and D/S/B;
2) Drain/Source float, cap voltage applied to Gate and Bulk connected to GND.

Say we use 2nd connection method to get an accumulation-mode NMOS cap (in a linear region), so from parasitic point of view, NMOS in NWELL will have more parasitic (due to NWELL to substrate cap) than NMOS in PWELL? I can think of NMOS in PWELL (no deep NWELL) has more noise because the all the noise will be injected to P-BULK. Am I right? Any other advantage/disadvantage? Any consideration from layout point of view?

Thanks,
Lynda

 

[Prashanthanilm]

Re: nmos in nwell gate capacitor

Thanks all for your reply.

To clarify the question for giri_lp, the NMOS caps I mentioned are not parasitic caps, they are sort of varicaps.

There are two kinds of connection methods:
1) Drain/Source/Bulk connected together, cap voltage applied to Gate and D/S/B;
2) Drain/Source float, cap voltage applied to Gate and Bulk connected to GND.

Say we use 2nd connection method to get an accumulation-mode NMOS cap (in a linear region), so from parasitic point of view, NMOS in NWELL will have more parasitic (due to NWELL to substrate cap) than NMOS in PWELL? I can think of NMOS in PWELL (no deep NWELL) has more noise because the all the noise will be injected to P-BULK. Am I right? Any other advantage/disadvantage? Any consideration from layout point of view?

Thanks,
Lynda

To which is given to which terminal? Like VDD/VSS?

 

[dick_freebird]

Re: What's the advantage & disadvantage of using NMOS and PMOS cap in analog IC circu

They both have a C-V swing and you may be best off using a pair to
get a more even capacitance across the common mode range, if
this is a concern. If you know the signal of interest will be close to
one rail then using the cap which is referred to the other, would
give you best density. However it's not a given that you really
want (say) a ground-referred signal shunted to the noisy supply
rail either.

A depletion mode MOSCAP has much nicer C-V, if you have one (they
can sometimes be made by, say, putting a NMOS S/D/G in an
N-well, but "digital" rules would call that an error despite it being
a useful and deliberate choice).

N MOSCAPs will have better access resistance (when strongly
inverted) owing to superior mobility. That improves Q some,
although if you cared primarily about Q you'd use something
else than a MOSCAP.

 

[Prashanthanilm]

Re: What's the advantage & disadvantage of using NMOS and PMOS cap in analog IC circu

More doubt!!

1>I was just wondering what if I place p-tap in nwell rather than n-tap and connect it to vdd.
2>Why we go for multiple contacts and why not for a big contact?(Resistance reduces, reliabity..blah blah...>BUT i want to know the basic important reason, what actually differentials)
3>Why tap is heavily doped? What if I place lightly doped.
4>Elaborate Substrate coupling noise and minority charge carrier noise ? And avoiding them using Guard rings?

And Lynda said about nmos in nwell as cap, mentioning to keep source and drain floating, Now whether this is practically possible? what about the substrate connection then ?
Thank you.