Hi,
I am new to this cadence tool. I am confused what is "partition" in it? I have divided my design into several sub-modules in verilog netlist after design compiler's synthesis. Do I still need to do partition in SOC encounter?
If your design is too large, please divided it. SOC encounter only support a way to do partition. Normally, do not divide a chip less 1M gates to some blocks. It will increase difficults to P&R.