AlexWan said:
Verification also do the functional compare between the RTL and gate-level netlist or placed netlist. And the pre-simualtion and post-simulation. So verification designer is also back-end design?
If you look at the job postings on monster.com for ASIC verification engineer, you will find out that verification usually means functional verification.
LVS (logic versus schematic) or formal verification (RTL vs. netlist) is usually part of the backend process.
Pre-simulation/post-simulation are commonly used in FPGA world. In ASIC, the counterparts are rtl sim and gate sim.
For complex design, verification is 70% of the total effort. It takes a lot of time to write a good testbench with all the verification components (in specman jargon eVC), develop numerous test cases and execute the test cases. It's a tough job.