What's different between VHDL and Verilog?

[yut]

What is the different of these 2 languages?
If I want to start which language,Do you think it's good for me.

 

[sp]

VHDL & verilog

choose which one is still the same... u are doing the digital system design... put tht in mind n both language write out the same hardware....

learn the fundamental of digital logic/system properly... n u will hav no prob on which language to use...

i learn VHDL ... it is superb but other say verilog... u see... hahhaha

comparison/preference on this 2 is not allowed here as there are too many posts on this matter already... there is a sticky for this 2 language comparison in the cpld/fpga section..

good luck...

my regards,
sp

 

[nafaiz]

Re: VHDL & verilog

verilog is easier to program but vhdl i think is recognized better. means that if u do programming in verilog and vhdl, the vhdl will be appreciated more.

 

[anjali]

Re: VHDL & verilog

what sp said is correct. main thing is the design. u can descrobe that in verilog or vhdl.

and all the frontend & backend tools supports both.

 

[bronzefury]

Re: VHDL & verilog

Go for Verilog and SystemVerilog for Designers.

 

[Summer.Xia]

VHDL & verilog

I love vrilog, which seems C language.

 

[nani_1981]

Re: VHDL & verilog

Hi,
verilog is easy to learn and code the design and but at some critical complex designs writing code in verilog is harder where as VHDL is a bit tough to learn but coding will be easy at any level.

bye.

 

[desaipa]

Re: VHDL & verilog

Hiiiiii,
Don’t get confused 1st decide in which language u want to do ur work.
But I think VHDL is bit easier than VERILOG to do work.
U can get so many tutorials on net.
U can design almost all circuits and simulations in VHDL.
But do anything at ur own interest.

PD

 

[trilogy]

Re: VHDL & verilog

using VHDL one can exactly model the hardware behavior , since VHDL contructs have very wide usage compared to verilog contructs.

 

[naveen reddy]

Re: VHDL & verilog

verilog and vhdl are the two most industry standard languages used presently

both the languages have there own strengths and capabilities
to start with verilog is good because it is similar to c language
if you know c language then you will feel verilog very easy.

vhdl is a bit difficult but has its own advantages

 

[anjali]

Re: VHDL & verilog

verilog is easy learning & used at industry level.

VHDL will be in a systematic way. & mostly used at reserch level, as it have more constructs than verilog. so hardware modelling will be exact. but complex to learn.

in industry both 50/50 usage.