What wrong with my SPI Communication?

[leblanc]

I just want to communicate whit a DAC above SPI but it don't walk like expected. can somebody help me pleas.

thanks




library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity sinus is

Port ( clk : in STD_LOGIC;
clk2_p: out std_logic;
SPI_MOSI : out std_logic;
SPI_SS_B : out std_logic;
AMP_CS : out std_logic;
AD_CONV: out std_logic;
SF_CEO: out std_logic;
FPGA_INIT_B : out std_logic;
--imput_word_t: out std_logic;
DAC_CS : out std_logic;
SPI_SCK : out std_logic;
SPI_MISO : in std_logic;
load : out STD_LOGIC
);

end sinus;

architecture Behavioral of sinus_574mhz is

signal shift_reg : std_logic_vector(11 downto 0):=(others => '0');
signal shift_reg1 : std_logic:='0';
signal zl: std_logic_vector(5 downto 0):=(others => '0');

signal sine: std_logic_vector(11 downto 0):=(others => '0');
signal stop: std_logic:='0';
signal temp: std_logic_vector(23 downto 0):=(others => '0');
constant ZERO : std_logic_vector(23 downto 0) := "000000000000000000000000";
signal CLK2 : std_logic:='0';
signal CLK3 : std_logic:='0';
signal serial_data: std_logic:='0';


component sinus
port (
CLK: IN std_logic;
SINE: OUT std_logic_VECTOR(11 downto 0));
end component;

begin
--imput_word_t <= clk2;

--adress <= "1111";
--command <= "0011";
--SPI_SCK <= clk3;
SPI_SS_B <= '1';
AMP_CS <= '1';
AD_CONV <= '0';
SF_CEO <= '1';
FPGA_INIT_B <= '1';
--imput_word <= command & adress & sine & "XXXX";
clk2_p <= clk2;

bloc_1 : sinus
port map (
CLK => CLK,
SINE => SINE);

process(clk2)
begin
if (clk2'event and clk2 = '0') then
SPI_SCK <= clk3;
if stop = '1' then
SPI_SCK <= '0';
end if;
end if;
end process;

-----------------------------------------------------------------------------

process(clk3, clk2)
begin
if clk2'event and clk2 = '1' then
if clk3 = '0' then
zl <= zl + 1;--command(4)
end if;
end if;
end process;

process(clk3, clk2)
begin
if clk2'event and clk2 = '1' then
if clk3 = '0' then
case zl is
when "000000" =>
DAC_CS <= '0';
stop <= '0';
SPI_MOSI <= '0';--data(23);
when "000001" =>
SPI_MOSI <= '0'; --data(23);
when "000010" =>
SPI_MOSI <= '1';-- data(23);
when "000011" =>
SPI_MOSI <= '1';-- data(23);
when "000100" =>
SPI_MOSI <= '1';-- data(23);
when "000101" =>
SPI_MOSI <= '1';-- data(23);
when "000110" =>
SPI_MOSI <= '1';--data(23);
when "000111" =>
SPI_MOSI <= '1';-- data(23);
when "001000" =>
SPI_MOSI <= shift_reg(11);--data(23);
when "001001" =>
SPI_MOSI <= shift_reg(11);-- data(23);
when "001010" =>
SPI_MOSI <= shift_reg(11);-- data(23);
when "001011" =>
SPI_MOSI <= shift_reg(11);-- data(23);
when "001100" =>
SPI_MOSI <= shift_reg(11); --data(23);
when "001101" =>
SPI_MOSI <= shift_reg(11);-- data(23);
when "001110" =>
SPI_MOSI <= shift_reg(11);-- data(23);
when "001111" =>
SPI_MOSI <= shift_reg(11);--data(23);
when "010000" =>
SPI_MOSI <= shift_reg(11);-- data(23);
when "010001" =>
SPI_MOSI <= shift_reg(11);-- data(23);
when "010010" =>
SPI_MOSI <= shift_reg(11);--data(23);
when "010011" =>
SPI_MOSI <= shift_reg(11);-- data(23);
when "010100" =>
SPI_MOSI <= 'X';-- data(23);
when "010101" =>
SPI_MOSI <= 'X';-- data(23);
when "010110" =>
SPI_MOSI <= 'X'; --data(23);
when "010111" =>
SPI_MOSI <= 'X';-- data(23);

when others => --DAC_CS <= '1'; --command_o<= 'X';
end case;

if zl ="011000" then
DAC_CS <= '1';
stop <= '1';

end if;
end if;
end if;
end process;

process(clk2)
begin
if rising_edge(clk2) then
temp <= temp(22 downto 0)& SPI_MISO;
shift_reg1 <= temp(23);
end if;
end process;

--------------------------------------------------------------------------------------------

process (CLK) is
variable var_zustand_vektor : std_logic_vector (1 downto 0):= "00";
variable var_zaehler_vektor : integer range 0 to 249:= 0;

begin


if (CLK'event AND CLK='1') then

CASE var_zustand_vektor is
when "00" =>
if var_zaehler_vektor = 124 then
var_zustand_vektor := "01";
else
var_zaehler_vektor := var_zaehler_vektor + 1;
CLK2 <= '1';
end if;
when "01" =>
if var_zaehler_vektor = 249 then
var_zustand_vektor := "00";
var_zaehler_vektor := 0;
else
var_zaehler_vektor := var_zaehler_vektor + 1;
CLK2 <= '0';
end if;
when others =>
var_zustand_vektor := "00";
End Case;

end if;
end Process;

process (CLK2) is
begin
if (CLK2'event AND CLK2='1') then
if (clk3 = '0') then
clk3 <= '1';
else
clk3 <= '0';
end if;
end if;
end Process;


---------------------------------------------------------------------------


process(clk2)
begin
if rising_edge(clk2) then
--load <= shift_reg(11);
shift_reg <= sine;
load <= shift_reg(11);
shift_reg(11 downto 1) <= shift_reg(10 downto 0);
end if;
end process;


end Behavioral;