What will happen if FIFO read clock is greater than FIFO write clock ?

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vlsi_freak

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What will happen if FIFO read clock is very much greater than FIFO write clock.
How will i synchronize such a case when the read domain requires continous read operation

Thanks in advance
 

Re: Read clk> wr_clk

your width of write port should be greater than read port by atleast as much times as the ratio of rd_clk_frq/wr_clk_frq.
 

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