No, if there is only a small square of overlap you run little to no risk. The only time I've seen noise issues is when a fast-moving line ran parallel and on top of a sensitive line for a long way.
You can calculate the parasitic capacitance between the lines by getting the capacitance per unit area data from your fab, and simply multiplying by the overlapping area.
For example, I had 250fF of parasitic capacitance, and the top line moved 30v in 20ns. Using I=C(dV/dt) this pushed 375uA of displacement current into the senstitive line. Rerouting the traces so they only had one small overlap reduced the parasitic capacitance to about 9fF and got rid of the noise issue.
Keep in mind that my sensitive line was an analog reference trace, not a digital output - a digital output would not be bothered by 375uA of coupling current.