You want the output to be high from the falling edge of 'A' until the falling edge of 'B'. You should be able to use a flip-flop or S-R latch to do that.
You want the output to be high from the falling edge of 'A' until the falling edge of 'B'. You should be able to use a flip-flop or S-R latch to do that.
Yes, I also attempted to achieve this using a NAND based latch. However, not able to generate the desired o/p signal. Not quite sure how to do that. Any help is appreciated. I guess, a simple latch will not help the cause; it may require a edge-triggered SR flip-flop, but I am not getting any suitable edge-triggered FF circuit.
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Your diagram is not clear.
* what happens to the opitput when B is HIGH during the falling edge of A?
* what happens to the opitput when A is LOW during the falling edge of B?
I need a real hardware, not a code!
So basically, the requirement is - o/p will be toggled to HIGH @negedge of i/p A and toggled to LOW @negedge of i/p B, o/p will not change its state @posedge of either A or B.
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Your diagram is not clear.
* what happens to the opitput when B is HIGH during the falling edge of A?
* what happens to the opitput when A is LOW during the falling edge of B?
* what happens to the opitput when B is HIGH during the falling edge of A?
This situation never occurs.
* what happens to the opitput when A is LOW during the falling edge of B?
this situation is already shown in the illustration given below.
So basically, let me explain one more time - the output should go to HIGH at the falling edge of 'A' and toggle to LOW at the next falling edge of 'B'.
Yes, sorry. I meant:
* what happens to the opitput when A is HIGH during the falling edge of B?
Do you have a high speed clock source?
What are the timing specifications:
* A_falling to output
* A LOW time
* A HIGH time
* B_falling to output
* B LOW time
* B HIGH time
* All A to B timings
You may use a PLD and a (high speed) clock.
The smallest - maybe one IC solution - could be a 8 pin microcontroller.
...it depends on your timing specifications.
Please provide an unequivocal function specification. The timing diagram in post #1 is useless because it doesn't show the state before and after the last input signal transition.
Please provide an unequivocal function specification. The timing diagram in post #1 is useless because it doesn't show the state before and after the last input signal transition.
But the waveform they used to simulate with in post #4 seems to indicate that the default state of A is high, the default state of B is low and the output should go high on falling edge of A and low on the falling edge of B.
I've been on the fence about answering this question. Not entirely sure if this is a homework problem or a real world problem they are trying to solve.
If it is homework, it's unfair to the rest of the students if you get your answer from a career engineer.
If it is your job, I have an issue with someone being hired to do a job they are not qualified to perform.
Because I like puzzles, I actually played around with this for 10 minutes yesterday and came up with two similar solutions.
One that requires a reset signal.
One that can self initialize but depending on the A and B initial state (a non-default state of A=1,B=0) it may have erroneous outputs until the first pulse occurs from then on it will be the correct output.
It might not be the best or most optimal solution, but I didn't spend a lot of time thinking about the problem. I'll give you a hint on what I did.
I used two falling edge D flip-flops and an XOR gate. Hmm actually that pretty much gives it away.