What will be synthesized after omission of unsynthesizable part of code

[FixitFast]

Dear all,

I know that unsynthizable code cannot be made into hardware. But while dealing looking at the PHY layer design of the MIG generated by Xilinx MIG I saw some un-synthesizable parts. My question is when transformed to hardware what will happen to the code or in other words will omitting the un-synth part, the hardware will be formed? Please see the snippet of the code

   process (clk)
   begin
      if (clk'event and clk = '1') then
         if (rst = '1') then
            init_complete_r <= '0' after (TCQ)*1 ps;
            init_complete_r1 <= '0' after (TCQ)*1 ps;
            init_complete_r2 <= '0' after (TCQ)*1 ps;
            dfi_init_complete <= '0' after (TCQ)*1 ps;
         else
            if (init_state_r = INIT_DONE) then
               init_complete_r <= '1' after (TCQ)*1 ps;
            end if;
            init_complete_r1 <= init_complete_r after (TCQ)*1 ps;
            init_complete_r2 <= init_complete_r1 after (TCQ)*1 ps;
            dfi_init_complete <= init_complete_r2 after (TCQ)*1 ps;
         end if;
      end if;
   end process;

 

[FvM]

Did you try to answer the question yourself by stripping of the timing statements?

Generally, timing statements are ignored in synthesis. If the code describes meaningful hardware, it can synthesize well, as the present example.

 

[TrickyDicky]

It could also be that this code represents the bahvioural model used when simulating. When it's actually synthesised, it uses a pre-compiled netlist.