What to use for circuit simulation: VHDL or Verilog?

[aman]

i need to simulate some circuits should i try verilog or vhdl

 

[maziaar83]

vhdl or verilog

I always use VHDL for simulating my digital circuits

 

[rajsrikanth]

Re: vhdl or verilog

its better to use verilog because verilog is easy to learn and implement and the code is synthesizable

 

[galatage]

Re: vhdl or verilog

if you know C well then verilog easy for you

 

[haidi.elbahr]

Re: vhdl or verilog

Hi
I think VHDL and Verilog are the same in the conecpt but with some differernces in statements but I prefere Verliog
BR

 

[echo47]

vhdl or verilog

Please read the forum rule:

 

[neils_arm_strong]

vhdl or verilog

better to use verilog>Its quick to learn and implement.

 

[bangash]

vhdl or verilog

go for verilog first.its easy

 

[Electronica]

vhdl or verilog

Verilog is a bit easier

 

[prashant_sharma]

Re: vhdl or verilog

know one .. u'll know the other..... Actually modelling and synthesis can be better achieved on a xilinx board using VHDL. so VHDL should be better, u'll know verilog if u r thorough with vhdl....