Concatenated the reject/rogue signals to make one register that then gets read into the cpu on the apb if an address (which is never used) is read. It hurts me to do this, just feels wrong, but it prevents synthesis purging the signal & thus I don't have to change my constraints or top level entity.
Ads-ee, unused IO get the following message
Warning: CMPG4-007: Top level port CAMLINK_1_DATA<15> is not connected to any IO pad.
Hi Tailor,
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