A RAM based search can only read and compare one RAM location per clock cycle. Respectively the search process can't be implemented in a function.
Hello,I tried to describe the Binary Search algorithm as follows, and it also takes a very long time while the synthesis. Is there any advice in the way of describing the code?
Thanks for all suggestions, I think that it is solved.The problem is yyou are trying to search the entire "ram" (this cannot now actually be a ram) in a single clock cycle. I suggest you draw out your intended circuit before you write any code for this. VHDL is not like writing software.
process (clk,rst) Variable L,R,M : integer; begin if (rst ='1') then L:= 0; R:=3871; elsif (clk'event and clk = '1') then if (L <= R) then M:= integer((L+R)/2); if(ram(M) < din) then L:= M+1; elsif ( ram(M) > din) then R:= M-1; else Location <= M; end if; else Location <= -1; end if; end if; end process; end Behavioral;
I tried but it failedThis will still have problems on the read side. You are doing asynchronous ram reads with no registered read address. It also does match the template provided. I suggest the ram read is done in another process and the ram read data is a separate register
process (clk,M) begin if (clk'event and clk = '1') then Read_M <= M; end if; d_ram <= RAM(Read_M); end process; process (clk,rst) begin if (rst ='1') then L<= 0; R<=3871; elsif (clk'event and clk = '1') then if (L <= R) then M<= integer((L+R)/2); if(d_ram < din) then L<= M+1; elsif ( d_ram > din) then R<= M-1; else Location <= Read_M; end if; else Location <= -1; end if; end if; end process; end Behavioral;
Yes, I read this tutorial: http://www.csit-sun.pub.ro/courses/Masterat/Xilinx Synthesis Technology/toolbox.xilinx.com/docsan/xilinx4/data/docs/xst/hdlcode14.htmldid you read how to write code to infer ram?