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What the best way to store data of size ( 90,000 * 32) bit (taken from a text file) using VHDL?

FvM

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A RAM based search can only read and compare one RAM location per clock cycle. Respectively the search process can't be implemented in a function.
 

FlyingDutch

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I tried to describe the Binary Search algorithm as follows, and it also takes a very long time while the synthesis. Is there any advice in the way of describing the code?
Hello,

try Vivado HLS (Hihg Level Syntthessis) and let the tool to convert this algorithm (C sources) into HDL version. The tool should make it parallel (as much as it is posssible).

Best Regards
 

MSAKARIM

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The problem is yyou are trying to search the entire "ram" (this cannot now actually be a ram) in a single clock cycle. I suggest you draw out your intended circuit before you write any code for this. VHDL is not like writing software.
Thanks for all suggestions, I think that it is solved.

Code:
process (clk,rst)

Variable L,R,M :  integer;
begin
if (rst ='1') then
L:= 0;
R:=3871;
    
elsif (clk'event and clk = '1') then

 if (L <= R) then
 M:= integer((L+R)/2);
 
 if(ram(M) < din) then
 L:= M+1;
 elsif ( ram(M) > din) then
  R:= M-1;
 else
  Location <= M;
 end if;
 
 else
  Location <= -1;
end if;

end if;
end process;

end Behavioral;
 

TrickyDicky

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This will still have problems on the read side. You are doing asynchronous ram reads with no registered read address. It also does match the template provided. I suggest the ram read is done in another process and the ram read data is a separate register
 

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Also don't use variables. Those variables will end up as combinational logic not registered logic as they are assigned immediately when reached.

Using variables usually makes for poorly performing pipelined designs.
 

MSAKARIM

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This will still have problems on the read side. You are doing asynchronous ram reads with no registered read address. It also does match the template provided. I suggest the ram read is done in another process and the ram read data is a separate register
I tried but it failed

Code:
process (clk,M)

begin

if (clk'event and clk = '1') then

Read_M <= M;

end if;

d_ram <= RAM(Read_M);

end process;



process (clk,rst)

begin

if (rst ='1') then

L<= 0;

R<=3871;

    

elsif (clk'event and clk = '1') then



 if (L <= R) then

 M<= integer((L+R)/2);

 

 if(d_ram < din) then

 

 L<= M+1;

 

 elsif ( d_ram > din) then

  R<= M-1;

 else

  Location <= Read_M;

 end if;

 

 else

  Location <= -1;

end if;



end if;

end process;

end Behavioral;
 

MSAKARIM

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Failed how? Error message, behaviour unexpected?
behaviour unexpected
when I tested it using one of the data that is already stored it gives me also "Location =-1" ?
 

TrickyDicky

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Did you read the synthesis guidelines yet? did you read how to write code to infer ram? have you also separately created a diagram showing the ram in your circuit with the appropraite address and control signals connected? It still feels like you are trying to write VHDL like software and just wrapped "if rising_edge(clk) then" around it. You need to think in terms of circuit elements and have a circuit diaram using known components in mind before you write any VHDL.
 

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IMO, it is best practice to put inferred RAM in it's own hierarchical block instead of in the middle of your code. This allows for inserting synthesis directives and attributes on the block to force synthesis to implement the type of RAM block you want. It also allows you to change the underlying code to match another vendors template if different. You can also just instantiate a vendor's IP block instead of inferring the RAM.

I think you should go back and look at the link in post #13 and find a inferred RAM that matches the behavior you want and place that code in a separate module, which you then instantiate in your code.
 

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