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I would probably add a small current in parallel with M0 to ensure that there is always "some" current in the amplifier. This will both startup the circuit and ensure some bandwidth for the internal nodes when operating with small output currents.
You can connect an NMOS in this fashion. Drain to drain of M6, source to the startup node(gate of M0). Connect the gate to a series of diode connected transistors down from vdd with a path to ground. What the whole set up does is that it pulls up gate node of M0, starts up a current in the whole path and when the circuit comes to stable current level, the start up NMOS will turn off. The diode connected transistors must be appropriately designed to switch off this start up NMOS.
Apart from that I am wondering how are u defining I1 and I2, as in what parameters define that.
To me, I would think that at bandgap circuit is needed together with a startup circuit to crank up the bandgap reference so as to hold the differential circuit at a constant biasing current. So if you would look up bandgap ciruit, I am quite certain you would find one with a startup circuit, after which you can then copy it.
I dont think a band gap is a must. Just defining the start up node voltage defines everything else. So you must think how you want to go about defining the node voltage. A simple resistor in the path of the current mirrors is a solution.
You can connect an NMOS in this fashion. Drain to drain of M6, source to the startup node(gate of M0). Connect the gate to a series of diode connected transistors down from vdd with a path to ground. What the whole set up does is that it pulls up gate node of M0, starts up a current in the whole path and when the circuit comes to stable current level, the start up NMOS will turn off. The diode connected transistors must be appropriately designed to switch off this start up NMOS.
Apart from that I am wondering how are u defining I1 and I2, as in what parameters define that.
I would look at the Gray/Meyers and Johns/Martin books' based start up circuit. What you would typically need is a very-weak PMOS load with NMOS driver, whose "output" branch is fed to one of the current reference circuit. The assumption is that the reference circuit has two stable "ref" current, 0 uA and Iref uA. The "weak-load" based circuit is always ON (mostly), and helps put-in some "leakage" current in the reference circuit so that it moves from 0 uA to Iref uA. The W/L for PMOS can be as simple as RECIPORCAL of W/L of PMOS used inthe reference circuit. Keep NMOS same. W/L do not really matter beyond some value.
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