Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

what should be concerned when design with 65nm process?

Status
Not open for further replies.

didibabawu

Member level 5
Joined
Dec 21, 2005
Messages
90
Helped
3
Reputation
6
Reaction score
0
Trophy points
1,286
Activity points
1,851
Can anyone tell me what should be concerned when design with 65nm process, and what is the difference between them.

Thank you very much
 

I haven't worked with this process, in general when working with a xx process you should concern:
- Understand EDR ( Electrical design Rule) where shown technology parameter like, gm, idsat, Bf, Cox, uo, breakdown, Cgso,delay...This document is provided by manufaturer.
- Scale down device dimension with previous process (company property)
- Simulation and see the phenomenon.

Regards
 

    didibabawu

    Points: 2
    Helpful Answer Positive Rating
What do you want to know exactly? Reliability?
65nm is no different from 90nm, 130nm ... except for higher metal fill density.
 

Leakage currents
Short channel effects
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top