What methods exist for division in FPGA

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matrixofdynamism

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What methods exist for division (fixed point) in FPGA and what are the advantages and disadvantages of each?
 

Easiest option is to use the divide core provided by the vendor - you get control over pipeline length and hence clock speed etc.
You could just use the divide function "/" if you dont care about the clock speed.
 
I am not sure if it will be your answer but there are some algorithms for division. Booth's algorithm is the hardest one to be implemented if you can implement it, the others would be easier to follow. However, it is hard to implement and you need to create a datapath for it (2 registers, 1 flop, 1 control unit, some muxes etc.). If you implement this, you will learn a lot though.
 
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