According to your description, it seems to be the "structural" Verilog.
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**broken link removed**
Verilog can be written in different abstract level:
1) Behavioral
2) RTL (Register Transfer Level)
3) Structural
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Example:
not a_inv (a_not, a); // assign a_not = ~a;
not b_inv (b_not, b); // assign b_not = ~b;
and a1 (x, a_not, b); // assign x = a_not & b;
and a2 (y, b_not, a); // assign y = b_not & a;
or out (c, x, y); // assign c = x | y;
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.... Anyone knows what's this format? And how to achieve this?
==> This kind of Verilog code may translated from the gate-level netlist of schematic-entry database.