Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
1. You read the routed netlist and the SPEF file in the primetime and perform post-routed timing analysis.
2. You read the routed netlist and the SPEF file and generate SDF[Standard Delay format] file. Use the routed netlist and SDF file for gate level simulation to check whether you are meeting functionality & timing.