Re: What is wrong with this Verilog code? Help! I am a newbi
I modified your code and is below
module normalize
(
input reset,
input clk,
input [7] img, //w.r.t u r code i am assuming these as 8bit
input [7] m, //w.r.t u r code i am assuming these as 8bit
input [7] v, //w.r.t u r code i am assuming these as 8bit
output reg nimg //
);
//state machine declaration
parameter S0 = 2'b00;
parameter S1 = 2'b01;
parameter S2 = 2'b10;
reg [1] y, Y; // This is 2bit a you have 3 satetes
//=============================================================================
//NS Logic
always@(reset or img or y or m or v)
begin
if (reset)
Y <= S0; //initial state
else
case
//
S0 : begin
if (img > m )
Y = S1;
else
Y = S2;
end
//
S1 : begin
Y = S0;
end
//
S2 : begin
Y = S0;
nimg=m+sqroot((v*(img-m)*(img-m))/v);
end
endcase
end
//=============================================================================
// output assign menr
always@(posedge clk)
begin
if (!reset)
nimg <= 1'b0; //assuming it is 1-bit
else
case
S0 : nimg <= nimg;
S1 : nimg <= m+sqroot((v*(img-m)*(img-m))/v);
S2 : nimg <= m+sqroot((v*(img-m)*(img-m))/v);
default : nimg <= nimg;
endcase
end
//=============================================================================
//state assign ment
always@(posedge clk or negedge reset)
begin
if (!reset)
y <= S0;
else
y <= Y;
end
//=============================================================================
endmodule
here i am assuming few things and coded it.. you need to find the componet for sqrroot and other if u get any errors
Added after 2 minutes:
Delete the nming code from the next logic... otherwise u will get multi-drive error
Added after 49 seconds:
module normalize
(
input reset,
input clk,
input [7:0] img, //w.r.t u r code i am assuming these as 8bit
input [7:0] m, //w.r.t u r code i am assuming these as 8bit
input [7:0] v, //w.r.t u r code i am assuming these as 8bit
output reg nimg //
);
//state machine declaration
parameter S0 = 2'b00;
parameter S1 = 2'b01;
parameter S2 = 2'b10;
reg [1:0] y, Y; // This is 2bit a you have 3 satetes
//=============================================================================
//NS Logic
always@(reset or img or y or m or v)
begin
if (reset)
Y <= S0; //initial state
else
case
//
S0 : begin
if (img > m )
Y = S1;
else
Y = S2;
end
//
S1 : begin
Y = S0;
end
//
S2 : begin
Y = S0;
end
endcase
end
//=============================================================================
// output assign menr
always@(posedge clk)
begin
if (!reset)
nimg <= 1'b0; //assuming it is 1-bit
else
case
S0 : nimg <= nimg;
S1 : nimg <= m+sqroot((v*(img-m)*(img-m))/v);
S2 : nimg <= m+sqroot((v*(img-m)*(img-m))/v);
default : nimg <= nimg;
endcase
end
//=============================================================================
//state assign ment
always@(posedge clk or negedge reset)
begin
if (!reset)
y <= S0;
else
y <= Y;
end
//=============================================================================
endmodule