Re: VHDL
Hi
VHDL is a acronym for:
(V) Hardware Description Language
(V) -> Very High Speed Integrated Circuits (VHSIC)
VHDL is belong to family of parallel languages calld HDL (Hardware Description Languages).
The most common languages in this methodoly are:
VHDL with IEEE STD 2002
Verilog with IEEE STD 2001
SystemC
SystemVerilog
Abel HDL
....
The most common tools and vendors in HDL are:
Modelsim (from Mentor Graphics)
Active-HDL from Aldec
VCS from Synopsys
NC-Verilog from Cadence
Verilog-XL from Cadence
The world of today is the world of co-existance not dominance!!!
You can convert your designs in Verilog into VHDL or vice versa
use:
X-HDL from X-Tek (VHDL <-> Verilog)
Analog Versus Digital:
HDL languages is now going into swallow the world of Analog and mixed-mode too.
Verilog-A and AMS trends in Verification, simulation and synthesis are going into the real facts.
The future:
How knows what future is clear?
I think object-oriented approaches and distributed simulation environments will be holded in the future HDL approaches.
tnx