What chandrakant says is correct if there is only one timescale precision (i.e. all 100ps). As soon there there are multiple precisions, it gets slightly more complicated.
It might help to understand that Verilog is defined with discrete event-driven simulation semantics. That means time is defined as an integer, and all signal changes (events) scheduled for a later time are put into queues. A queue for a discrete time in the future is created as soon as an event needs to be scheduled for that time. As soon as all the events for the current time are finished, the simulator looks for the next time when an event is scheduled, advances the current time to that next time, and the process repeats until there is nothing left to do, or it executes a $finish. Time is discrete because the simulator only executes the times where events are scheduled, and skips over everything else. So you could have a simulation that executes at times 0,2,5,10,15,20,25,26.
The simulator knows nothing about seconds or nanoseconds, only unit-less integers.
In order to synchronize the scheduling of events across different timescales and precisions, the simulator picks the smallest time precision across the entire design and assigns that the value of 1 time unit. If the smallest precision was 10ps, that becomes the global value of 1 time unit. In the example above, there would be one more scaling applied as the entire design was elaborated, and #10.10 would become a delay of 10100 units. So the statement clk_1 = !clk_1 would be scheduled 10100 units into the future.