Jun 6, 2012 #1 K krishnakanth.ramireddy Newbie level 3 Joined Mar 7, 2012 Messages 4 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Location bangalore Activity points 1,305 what is the working of cmos inverter when gate input voltage is fed to VDD/2?
Jun 6, 2012 #2 ALERTLINKS Advanced Member level 4 Joined Dec 13, 2003 Messages 1,258 Helped 396 Reputation 786 Reaction score 380 Trophy points 1,363 Location Pakistan Activity points 7,263 https://www.edaboard.com/threads/198656/ - - - Updated - - -
Jun 6, 2012 #3 V varunkant2k Full Member level 6 Joined Nov 15, 2011 Messages 363 Helped 59 Reputation 118 Reaction score 57 Trophy points 1,308 Location India Activity points 3,316 Depending upon the Quiescent point, IF both transistors have symmetric sizing (both transistors will be on) ,output will be VDD/2.
Depending upon the Quiescent point, IF both transistors have symmetric sizing (both transistors will be on) ,output will be VDD/2.