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What is the use of generate statement here ?

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vizpal

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I have the following code...

genvar 1;
generate
for (i = 0; i < num_chan; i = i+1)
begin : loop_label
a1 : assert property(p_req_gets_resp(i));
if (i < 5)
c1 : cover property (p_max_latency(i));
end
endgenerate


My Doubt is --> What is the use of generate statement here ??? How does it differ from the for loop???
 

vizpal

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Re: Generate Statement

Any realtion to vhdl Generate..??? :?:
 

walid farid

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Re: Generate Statement

Hi,
The Generate Statement in Verilog differs from the for loop, that it adds a specific parts of verilog code to the module depending on the conditions, which helps that the code in a module ---> Instance functionality , can be variable according to the parameter passed to the module for example.
 

venkatesankalidass

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Re: Generate Statement

in generate model instantion is possible but in loop it is not possible
 

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