What is the synthesis of this rtl?

[sun_ray]

What will the my_signal synthesize to in the following code?

always (*)
begin
if (I1 == 0) my_signal <= 1'b1
else if (I2 == 0) my_signal <= 1'b0
end

 

[FvM]

Re: synthesis of this rtl

To a RS latch.

 

[sun_ray]

Re: synthesis of this rtl

To a RS latch.

Will not the synthesis tool take the other conditions for I1 and I2 as X because the else condition is not defined here? How do the synthesis tool generate a latch because other conditions for I1 and I2 are not defined.

What will the following code synthesize to

always (*)
begin
if (I1 == 0)
begin
my_signal <= 1'b1
my_signal <= 1'b0
end
else
begin
my_signal <= 1'b0
my_signal <= 1'b1
end
end

Can you please provide a document that describe this basic code?

Can you also reply to my thread titled FIFO and clock domain crossing? This thread was raised a few days back.

Regards

 

[bright8848]

Re: synthesis of this rtl

I have the same puzzle. By the way, what's difference between block assignment and non-block assignment in combin logic? Thank you very much~

 

[sun_ray]

Re: synthesis of this rtl

I have the same puzzle. By the way, what's difference between block assignment and non-block assignment in combin logic? Thank you very much~

There is a SNUG paper on block abd non blocking assignment. Please search and read it.

 

[FvM]

Re: synthesis of this rtl

Will not the synthesis tool take the other conditions for I1 and I2 as X because the else condition is not defined here? How do the synthesis tool generate a latch because other conditions for I1 and I2 are not defined.

The code does not specify an assigned value for the condition (I1 == 1 && I2 == 1), so the previous value must be preserved, in other words a latch is generated. The value is not undefined.

 

[jt_eaton]

Re: synthesis of this rtl

The always@(*) will only execute when any of the input variables change. Since your inputs are all constants this rtl will never execute and synthesis should not produce anything

 

[bright8848]

Re: synthesis of this rtl

Hi Sun_ray, would you please give me a link for this document? Thank you~

 

[sun_ray]

Re: synthesis of this rtl

FvM

The value is not undefined.

What do you mean by undefined? Do you want to mean the don't care X?

The code does not specify an assigned value for the condition (I1 == 1 && I2 == 1), so the previous value must be preserved, in other words a latch is generated.

It is agreed that the code does not provide assigned values when I1 == 1 and also when I2 == 1. How do you say in this case the previous value must be preserved? The code does not say that when I1 == 1, my_signal will have to preserve the previous value and the code also does not specify when I2 == 1, my_signal will have to preserve the previous value.

Can you please let me know what the following code synthesizes to? I corrected the earlier RTL in post no. 3, by changing the my_signal to my_signal1 and my_signal2.

always (*)
begin
if (I1 == 0)
begin
my_signal1 <= 1'b1
my_signal2 <= 1'b0
end
else
begin
my_signal1 <= 1'b0
my_signal2 <= 1'b1
end
end

Regards

- - - Updated - - -

The always@(*) will only execute when any of the input variables change. Since your inputs are all constants this rtl will never execute and synthesis should not produce anything

jt_eaton
Which RTL are you talking of? Is this the first rtl in post no. 1 or the second rtl in post no. 3? The rtl in post no. 3 is corrected at post no. 9.
Regards
- - - Updated - - -

Hi Sun_ray, would you please give me a link for this document? Thank you~

bright8848

This is an usually available paper in Google. Please search in Google with the necessary keywords, I provided.

Regards

 

[jt_eaton]

Re: synthesis of this rtl

My mistake, I forgot about the other variables that do change. So the code is legal.

 

[FvM]

Re: synthesis of this rtl

Do you understand that the below behavioral statement describes a latch (hold the previous state while en == 0)?

always (*)
  if (en) o <= i;

Then you should easily identify the latch in your post #1 code.

The code in post #9 isn't but a long winded way to write

my_signal1 <= !I1;
my_signal2 <= I1;

 

[sun_ray]

Re: synthesis of this rtl

FvM

Do you understand that the below behavioral statement describes a latch (hold the previous state while en == 0)?

always (*)
  if (en) o <= i;

I know that the above code will synthesize to a latch. But the question here also remains how the above rtl specify to preserve the value when en == 0, because the above rtl does not specify anything when en == 0. Please answer this.

The code in post #9 isn't but a long winded way to write

What do you want to mean by stating that the code in post #9 isn't? What do you mean by isn't? Do you want to mean that the code in post no. # 9 is not a latch.

Regards

 

[FvM]

Re: synthesis of this rtl

But the question here also remains how the above rtl specify to preserve the value when en == 0, because the above rtl does not specify anything when en == 0.

For input conditions that don't specify an assigned value, the previous value will be preserved. In other words a latch is generated. Your Verilog textbooks should tell about this.

Do you want to mean that the code in post no. # 9 is not a latch.

Indeed it's no latch. I already told what it is.

P.S.: The preservation of the previous value in incomplete conditional branches can be concluded from the general Verilog language specification.

6.2 Procedural assignments

The primary discussion of procedural assignments is in 9.2. However, a description of the basic ideas in this clause highlights the differences between continuous assignments and procedural assignments.

As stated in 6.1, continuous assignments drive nets in a manner similar to the way gates drive nets. The expression on the right-hand side can be thought of as a combinatorial circuit that drives the net continuously. In contrast, procedural assignments put values in variables. The assignment does not have duration; instead, the variable holds the value of the assignment until the next procedural assignment to that variable.

The conclusions for hardware modelling are discussed in many Verilog textbooks and tutorials, e.g. ;

 

[sun_ray]

Re: synthesis of this rtl

FvM

Thanks for the replies.

Indeed it's no latch. I already told what it is.

Do you want to mean that mysignal1 is the output of an inverter with I1 as the input and my_signal is a buffer with I1 as the input?

CAN YOU PLEASE PROVIDE A DOCUMENT OR LINK THAT DESCRIBES THIS KIND OF BASIC RTLs LIKE LATCH AND OTHER BASIC DESIGNS?

Regards

 

[FvM]

Re: synthesis of this rtl

Do you want to mean that mysignal1 is the output of an inverter with I1 as the input and my_signal is a buffer with I1 as the input?

Yes, a complete conditional branch with complete output assignments in a level sensitive always block models combinational logic, in this case a simpler buffer respectively inverter.

I personally prefer the Verilog LRM IEEE 1364 (or System Verilog IEEE 1800, which includes basic Verilog as a subset) and the standard for synthesizable Verilog IEEE 1364.1 as reference. But as said, the topics are also presented in most text books.

 

[sun_ray]

Re: synthesis of this rtl

I personally prefer the Verilog LRM IEEE 1364 (or System Verilog IEEE 1800, which includes basic Verilog as a subset) and the standard for synthesizable Verilog IEEE 1364.1 as reference. But as said, the topics are also presented in most text books.

But there they describes the verilog language. different latches or other small designs. The LRM does not describe rtls of basic designs like I requested you to providde a document that describes rtls for different kind of latches and other basic rtls. Please note my question again below.

CAN YOU PLEASE PROVIDE A DOCUMENT OR LINK THAT DESCRIBES THIS KIND OF BASIC RTLs LIKE LATCH AND OTHER BASIC DESIGNS?

Regards

 

[FvM]

Re: synthesis of this rtl

I don't agree, basically it's all in the LRM. Some RTL specific points are clarified in 1364.1 IEEE Standard for Verilog® Register Transfer Level Synthesis.

 

[sun_ray]

Re: synthesis of this rtl

I don't agree, basically it's all in the LRM. Some RTL specific points are clarified in 1364.1 IEEE Standard for Verilog® Register Transfer Level Synthesis.

I saw the IEEE Std 1364 LRM. I did not find the code for SR latch which we described at post number 1 in this thread.
Can you please let me know the section and the page numbers in that LRM where it is described?

Are some of the rtl specific points which are described in 1364.1 IEEE Standard for Verilog® Register Transfer Level Synthesis, also present in IEEE Std 1364 LRM-2005?

Regards