What is the syntax error in the verilog prog in declaring the s and d as arrays.

[sairasalim]

module split(x,s,d,N);
input [4:0]x[4:0];
input N=4;
inout [4:0]s[0:4];
inout [4:0]d[0:4];
reg [4:0]s[0:4];
reg [4:0]d[0:4];
reg i,j;
initial
begin
for(i=0,i<N,i=i+1)
begin
for(j=0,j<N,j=j+1)
begin
if(j%2== 0)
s[j]=x[j];
else
d[j]=x[j];
end
end
end
endmodule


The syntax error shown was
Error: D:/II SEMESTER/project/split.v(6): 'Port' must not be declared to be an array: s.
** Error: D:/II SEMESTER/project/split.v(7): 'Port' must not be declared to be an array: d.
** Error: D:/II SEMESTER/project/split.v(11): near "<": syntax error, unexpected '<'

 

[FvM]

'Port' must not be declared to be an array

That's by Verilog specification. Check your text book, probably use System Verilog to overcome the restriction.

Furthermore there's a problem with the type of i,j and N.