What is the switch activity in CMOS?

[Alexander Yin]

I have not found any basic answer to this question. Can anybody tell me what's that in CMOS power consumption?

Thanks a lot.

 

[Johnson]

cnsider a d type flip-flop, clock and d are its inputs and q is output. activity mean how many times data is changing or toggleing with in 100 clock pulse event. actually data change will force q to change and you know that state change nedds power.
Pav=a.C.Vdd^2, it make sense that with higher toggeling rate of data, dissipated power will rise!
each low-power design book talk about this issue!

 

[Alexander Yin]

It's a very clear explanation. Thank you for helping.

cnsider a d type flip-flop, clock and d are its inputs and q is output. activity mean how many times data is changing or toggleing with in 100 clock pulse event. actually data change will force q to change and you know that state change nedds power.
Pav=a.C.Vdd^2, it make sense that with higher toggeling rate of data, dissipated power will rise!
each low-power design book talk about this issue!

 

[cesare]

In a CMOS structure there is no steady state current flow because only one of the two switches is on.

However during the switching transient the output/load capacitance must be charged/discharged and both switches can be on at the same time for a short time.

So CMOS structure dissipate power only when switches and power consumption is proportional to switching frequency

 

[Johnson]

You you must know that in DSM(90nm, 65nm) gate lekage and subthreshold current are also very important, and dissipate power.